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3-Channel Digital Potentiometer with Nonvolatile Memory ADN2860
FEATURES
3 channels: Dual 512-position Single 128-position 25 k or 250 k full-scale resistance Low temperature coefficient: Potentiometer divider 15 ppm/C Rheostat mode 35 ppm/C Nonvolatile memory retains wiper settings Permanent memory write protection Linear increment/decrement 6 dB increment/decrement I2C-compatible serial interface 2.7 V to 5.5 V single-supply operation 2.25 V to 2.75 V dual-supply operation Power-on reset time 256 bytes general-purpose user EEPROM 11 bytes RDAC user EEPROM GBIC and SFP compliant EEPROM 100-year typical data retention at TA = 55C
VDD VSS DGND SCL SDA AD0 AD1 A0_EE A1_EE COMMAND DECODE LOGIC POWER-ON RESET ADDRESS DECODE LOGIC DECODE LOGIC I2C SERIAL INTERFACE
FUNCTIONAL BLOCK DIAGRAM
RDAC0 REGISTER
256 BYTES USER EEPROM 32 BYTES RDAC EEPROM DATA CONTROL RDAC0 A0 W0 9 BITS RDAC1 B0
RDAC1 REGISTER
A1 W1
9 BITS RDAC2
B1
RDAC2 REGISTER
A2 W2
RESET
7 BITS
B2
03615-001
WP
Figure 1.
APPLICATIONS
Laser diode drivers Optical amplifiers TIA gain setting TEC controller temperature setpoint
GENERAL DESCRIPTION
The ADN2860 provides dual 512-position and single 128-position, digitally controlled variable resistors1 (VR) in a single 4 mm x 4 mm LFCSP package. This device performs the same electronic adjustment function as a potentiometer, trimmer, or variable resistor. Each VR offers a completely programmable value of resistance between the A terminal and the wiper, or the B terminal and the wiper. The fixed A-to-B terminal resistance of 25 k or 250 k has a 1% channel-tochannel matching tolerance and a nominal temperature coefficient of 35 ppm/C. Wiper position programming, EEPROM2 reading, and EEPROM writing are conducted via the standard 2-wire I2C interface. Previous default wiper position settings can be stored in memory, and refreshed upon system power-up. Additional features of the ADN2860 include preprogrammed linear and logarithmic increment/decrement wiper changing. The actual resistor tolerances are stored in EEPROM so that the actual end-to-end resistance is known, which is valuable for calibration in precision applications. The ADN2860 EEPROM, channel resolution, and package size conform to GBIC and SFP specifications. The ADN2860 is available in a 4 mm x 4 mm, 24-lead LFCSP package. All parts are guaranteed to operate over the extended industrial temperature range -40C to +85C.
1
2
The terms programmable resistor, variable resistor, RDAC, and digital potentiometer are used interchangeably. The terms nonvolatile memory, EEMEM, and EEPROM are used interchangeably.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
ADN2860 TABLE OF CONTENTS
Electrical Characteristics ................................................................. 3 Electrical Characteristics ................................................................. 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 Interface Descriptions.................................................................... 10 I2C Interface ................................................................................ 10 EEPROM Interface..................................................................... 11 RDAC I2C Interface.................................................................... 12 Theory of Operation ...................................................................... 15 Linear Increment and Decrement Commands ...................... 15 Logarithmic Taper Mode Adjustment (6 dB/step) .............. 15 Using Additional Internal Nonvolatile EEPROM.................. 16 Digital Input/Output Configuration........................................ 16 Multiple Devices on One Bus ................................................... 16 Level Shift for Bidirectional Communication ........................ 16 Terminal Voltage Operation Range ......................................... 16 Power-Up Sequence ................................................................... 17 Layout and Power Supply Biasing ............................................ 17 RDAC Structure.......................................................................... 17 Calculating the Programmable Resistance ............................. 17 Programming the Potentiometer Divider............................... 18 Applications..................................................................................... 19 Laser Diode Driver (LDD) Calibration................................... 19 Outline Dimensions ....................................................................... 20 Ordering Guide .......................................................................... 20
REVISION HISTORY
11/04--Rev. 0 to Rev. A Changes to Ordering Guide .......................................................... 20 7/04--Revision 0: Initial Version
Rev. A | Page 2 of 20
ADN2860 ELECTRICAL CHARACTERISTICS
Single supply: VDD = 2.7 V to 5.5 V and -40C < TA < +85C, unless otherwise noted. Dual supply: VDD = +2.25 V or +2.75 V, VSS = -2.25 V or -2.75 V, and -40C < TA < +85C, unless otherwise noted. Table 1.
Parameter DC CHARACTERISTICS, RHEOSTAT MODE Resistor Differential Nonlinearity2 Symbol Conditions Min Typ1 Max Unit
R-DNL Resistor Integral Nonlinearity2 R-INL R-INL R-INL Resistance Temperature Coefficent Wiper Resistance Channel Resistance Matching Nominal Resistor Tolerance DC CHARACTERISTICS, POTENTIOMETER DIVIDER MODE Differential Nonlinearity3
(RWB/RWB)/T x 106
RWB, 7-bit channel RWB, 9-bit channels RWB, 7-bit channel RWB, 9-bit channels, VDD = 5.5 V RWB, 9-bit channels, VDD = 2.7 V VDD = 5 V, IW = 1 V/RWB VDD = 3 V, IW = 1 V/RWB Ch 1 and Ch 2 RWB, Dx = 0x1FF Dx = 0x3FF
-0.75 -2.5 -0.5 -2.0 -4.0 35 100 250 0.1 -15
+0.75 +2.5 +0.5 +2.0 +4.0 150 400 +15
LSB LSB LSB LSB LSB ppm/C % %
RW RAB1/RAB2 RAB/RAB
DNL DNL Integral Nonlinearity3 INL INL (VW/VW)/T x 106 VWFSE VWZSE
7-bit channel 9-bit channels 7-bit channel 9-bit channels Code = half scale 7-bit channel/9-bit channels, code = full scale 7-bit channel/9-bit channels, code = zero scale
-0.5 -2.0 -0.5 -2.0 15 -1/-2.75 0/0
+0.5 +2.0 +0.5 +2.0
LSB LSB LSB LSB ppm/C LSB LSB
Voltage Divider Temperature Coefficent Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Terminal Voltage Range4 Capacitance5 Ax, Bx Capacitance5 Wx Common-Mode Leakage Current5, 6 DIGITAL INPUTS AND OUTPUTS Input Logic High
0/0 1/2.0
VA, B, W CA,B CW ICM VIH
VSS f = 1 kHz, measured to GND, code = half scale f = 1 kHz, measured to GND, code = half scale VW = VDD/2 VDD = 5 V, VSS = 0 V VDD/VSS = +2.7 V/0 V or VDD/VSS = 2.5 V VDD = 5 V, VSS = 0 V VDD/VSS = +2.7 V/0 V or VDD/VSS = 2.5 V RPULL-UP = 2.2 k to VDD = 5 V, VSS = 0 V RPULL-UP = 2.2 k to VDD = 5 V, VSS = 0 V WP = VDD A0 = GND 2.4 2.1 85 95 0.01
VDD
V pF pF
1
A V V
Input Logic Low
VIL
0.8 0.6 4.9 0.4 9 3
V V V V A A
Output Logic High (SDA) Output Logic Low WP Leakage Current A0 Leakage Current
VOH VOL IWP IA0
Rev. A | Page 3 of 20
ADN2860
Parameter Input Leakage Current (Excluding WP and A0) Input Capacitance5 POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Positive Supply Current Negative Supply Current EEMEM Data Storing Mode Current EEMEM Data Restoring Mode Current Power Dissipation7 Power Supply Sensitivity5 Symbol II CI VDD VDD/VSS IDD ISS IDD_STORE IDD_RESTORE PDISS PSS VSS = 0 V VIH = VDD or VIL = GND, VSS = 0 V VIH = VDD or VIL = GND, VDD = 2.5 V, VSS = -2.5 V VIH = VDD or VIL = GND VIH = VDD or VIL = GND VIH = VDD = 5 V or VIL = GND VDD = 5 V 10% 2.7 2.25 5 -5 35 2.5 25 0.01 Conditions VIN = 0 V or VDD Min Typ1 Max 1 Unit A pF 5.5 2.75 15 -15 V V A A mA mA W %/%
5
75 0.025
1 2
Typical represents average readings at 25C, VDD = 5 V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. 3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. 4 Resistor Terminals A, B, and W have no limitations on polarity with respect to each other. 5 Guaranteed by design and not subject to production test. 6 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 7 PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation.
t8
SDA
t1 t8 t9 t6
SCL
P
S
t3
t5
S
t7
P
t10
Figure 2. I2C Timing Diagram
Rev. A | Page 4 of 20
03615-015
t2
t4
ADN2860 ELECTRICAL CHARACTERISTICS
Single Supply: VDD = 3 V to 5.5 V and -40C < TA < +85C, unless otherwise noted. Dual Supply: VDD = +2.25 V or +2.75 V, VSS = -2.25 V or -2.75 V, and -40C < TA < +85C, unless otherwise noted. Table 2.
Parameter DYNAMIC CHARACTERISTICS 2, 3 Bandwidth -3 dB Total Harmonic Distortion VW Settling Time Symbol BW THDW tS Conditions VDD/VSS = 2.5 V, RAB = 25 k/250 k. VA = 1 V rms, VB = 0 V, f = 1 kHz. VA = VDD, VB = 0 V, VW = 0.50% error band,
code = 0x000 to 0x100, RAB = 25 k/250 k.
Min
Typ1 125/12 0.05 4/36
Max
Unit kHz % s
Resistor Noise Spectral Density Digital Crosstalk
eN_WB CT
Analog Crosstalk INTERFACE TIMING CHARACTERISTICS (Apply to All Parts)4, 5 SCL Clock Frequency tBUF Bus Free Time between Stop and Start tHD;STA Hold Time (Repeated Start) tLOW Low Period of SCL Clock tHIGH High Period of SCL Clock tSU;STA Setup Time for Start Condition tHD;DAT Data Hold Time tSU;DAT Data Setup Time tR Rise Time of Both SDA and SCL Signals tF Fall Time of Both SDA and SCL Signals tSU;STO Setup Time for Stop Condition EEMEM Data Storing Time EEMEM Data Restoring Time at Power-On EEMEM Data Restoring Time on Restore Command or Reset Operation EEMEM Data Rewritable Time FLASH/EE MEMORY RELIABILITY Endurance6 Data Retention7
CAT
RAB = 25 k/250 k, TA = 25C. VA = VDD, VB = 0 V, measure VW with adjacent RDAC making full-scale change. Signal input at A0 and measure output at W1, f = 1 kHz.
14/45 -80
nVHz dB
-72
dB
fSCL t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 tEEMEM_STORE tEEMEM_RESTORE1 tEEMEM_RESTORE2 tEEMEM_REWRITE
400 After this period, the first clock pulse is generated. 1.3 600 1.3 0.6 600 100 300 300 600 26 360 360 540 100 55C. 100
kHz s ns s s ns ns ns ns ns ns ms s s s kcycles years
50 900
1 2
Typical represents average readings at 25C, VDD = 5 V. All dynamic characteristics use VDD = 5 V. 3 Guaranteed by design and not subject to production test. 4 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 5 See Figure 2 for the location of measured values. 6 Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 Method A117 and measured at -40C, +25C, and +85C. Typical endurance at 25C is 700,000 cycles. 7 Retention lifetime equivalent at junction temperature (TJ) = 55C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates with junction temperature.
Rev. A | Page 5 of 20
ADN2860 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 3.
Parameter VDD to GND VSS to GND VDD to VSS VA, VB, VW to GND IA, IB, IW Intermittent1 Continuous Digital Inputs and Output Voltage to GND Operating Temperature Range2 Maximum Junction Temperature (TJ max) Storage Temperature Lead Temperature, Soldering Vapor Phase (60 s) Infrared (15 s) Thermal Resistance Junction-to-Ambient JA, LFCSP-24 Rating -0.3 V, +7 V +0.3 V, -7 V 7V VSS - 0.3 V, VDD + 0.3 V 20 mA 2 mA -0.3 V, VDD + 0.3 V -40C to +85C 150C -65C to +150C 215C 220C
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
32C/W
1 2
Includes programming of nonvolatile memory. Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 6 of 20
ADN2860 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD0 AD1 A0_EE A1_EE TEST0 (NC) TEST1 (NC)
RESET WP SCL SDA DGND VSS
1 2 3 4 5 6
24 23 22 21 20 19
PIN 1 INDICATOR
AD2860
TOP VIEW (Not to Scale)
18 17 16 15 14 13
TEST2 (NC) TEST3 (NC) VDD A0 W0 B0
7 8 9 10 11 12
NC = NO CONNECT
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Mnemonic RESET WP SCL SDA DGND VSS A2 W2 B2 A1 W1 B1 B0 W0 A0 VDD TEST3 TEST2 TEST1 TEST0 A1_EE A0_EE AD1 AD0 Description Resets the scratchpad register with current contents of the EEMEM register. Factory defaults to midscale before any programming. Write Protect. When active low, WP prevents any changes to the present register contents, except that RESET and Commands 1 and 8 still refresh the RDAC register from EEMEM. Serial Input Register Clock. Shifts in one bit at a time upon the positive clock edges. Serial Data Input. Shifts in one bit at a time upon the positive edges. The MSB is loaded first. Ground. Logic ground reference. Negative Supply. Connect to 0 V for single-supply applications. A Terminal of RDAC2. Wiper Terminal of RDAC2. B Terminal of RDAC2. A Terminal of RDAC1. Wiper Terminal of RDAC1. B Terminal of RDAC1. B Terminal of RDAC0. Wiper Terminal of RDAC0. A Terminal of RDAC0. Positive Power Supply. Test Pin 3. Do not connect. Test Pin 2. Do not connect. Test Pin 1. Do not connect. Test Pin 0. Do not connect. I2C Device Address 1 for EEMEM. I2C Device Address 0 for EEMEM. I2C Device Address 1 for RDAC. I2C Device Address 0 for RDAC.
Rev. A | Page 7 of 20
03615-014
A2 W2 B2 A1 W1 B1
ADN2860 TYPICAL PERFORMANCE CHARACTERISTICS
1.0 0.8 0.6 0.4 TA = -40C, +25C, +85C SUPERIMPOSED VDD = 5V 1.0 0.8 0.6 0.4
INL (LSB)
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 64 128 192 256 320 384 448 512
03615-002
R-DNL (LSB)
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 TA = -40C, +25C, +85C SUPERIMPOSED VDD = 5V 64 128 192 256 320 384 448 512
03615-005 03615-007 03615-006
CODE (DECIMAL)
CODE (DECIMAL)
Figure 4. INL--9-Bit RDAC
Figure 7. R-DNL--9-Bit RDAC
1.50 1.25 1.00 0.75 0.50 TA = -40C, +25C, +85C SUPERIMPOSED VDD = 5V
0.5 0.4 0.3 0.2 TA = -40C, +25C, +85C SUPERIMPOSED VDD = 5V
DNL (LSB)
INL (LSB)
0 64 128 192 256 320 384 448 512
03615-003
0.25 0 -0.25 -0.50 -0.75 -1.00 -1.25 -1.50 CODE (DECIMAL)
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 16 32 48 64 80 96 112 128 CODE (DECIMAL)
Figure 5. DNL--9-Bit RDAC
Figure 8. INL--7-Bit RDAC
1.0 0.8 0.6 0.4 TA = -40C, +25C, +85C SUPERIMPOSED VDD = 5V
0.5 0.4 0.3 0.2 TA = -40C, +25C, +85C SUPERIMPOSED VDD = 5V
R-INL (LSB)
0 -0.2 -0.4 -0.6 -0.8 -1.0 0 64 128 192 256 320 384 448 512
03615-004
DNL (LSB)
0.2
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 16 32 48 64 80 96 112 128
CODE (DECIMAL)
CODE (DECIMAL)
Figure 6. R-INL--9-Bit RDAC
Figure 9. DNL--7-Bit RDAC
Rev. A | Page 8 of 20
ADN2860
0.5 0.4 0.3 0.2 50
POTENTIOMETER MODE TEMPCO (ppm/C)
TA = -40C, +25C, +85C SUPERIMPOSED VDD = 5V
45 40 35 30 25 20 15 10 5 0 0
TA = -40C, +85C VDD = 5V VA = VDD VB = 0V
R-INL (LSB)
0.1 0 -0.1 -0.2 -0.3 -0.4
03615-008
-0.5 0 16 32 48 64 80 96 112 128 CODE (DECIMAL)
64
128
192
256
320
384
448
512
CODE (DECIMAL)
Figure 10. R-INL--7-Bit RDAC
Figure 13. Temperature Coefficient (Potentiometer Mode)
0.5 0.4 0.3 0.2 TA = -40C, +25C, +85C SUPERIMPOSED VDD = 5V
10 8 IDD: VDD = 5.5V 6
SUPPLY CURRENT (mA)
4 2 IDD: VDD = 2.7V 0 -2 -4 -6 -8 IS: VDD = 2.7V, VSS = 2.7V
R-DNL (LSB)
0.1 0 -0.1 -0.2 -0.3 -0.4
03615-009
-0.5 0 16 32 48 64 80 96 112 128 CODE (DECIMAL)
-20
0
20
40
60
80
100
120
140
TEMPERATURE (C)
Figure 11. R-DNL--7-Bit RDAC
Figure 14. Supply Current vs. Temperature
50 45 TA = -40C, +85C VDD = 5V VA = VDD VB = 0V
110 100 90 TA = 25C
RHEOSTAT MODE TEMPCO (ppm/C)
40 35
25 20 15
IDD (mA)
30
80 70 60 50 VDD = 5.5V VDD = 2.7V
10 5
03615-010
40 30 1 101 102 103 104
0
64
128
192
256
320
384
448
512
105
106
107
CODE (DECIMAL)
CLOCK FREQUENCY (Hz)
Figure 12. Temperature Coefficient (Rheostat Mode)
Figure 15. Supply Current vs. Clock Frequency
Rev. A | Page 9 of 20
03615-013
0
03615-012
-10 -40
03615-011
ADN2860 INTERFACE DESCRIPTIONS
I2C INTERFACE
All control and access to both EEPROM memory and the RDAC registers are conducted via a standard 2-wire I2C interface. Figure 2 shows the timing characteristics of the I2C bus. Figure 16 and Figure 17 illustrate standard transmit and receive bus signals in the I2C interface. These figures use the following legend:
From master to slave From slave to master S = Start condition P = Stop condition A = Acknowledge (SDA low) A = Not acknowledge (SDA high) R/W = Read enable at high and write enable at low
S SLAVE ADDRESS R/W A DATA A DATA A/A P
03615-016
0 = WRITE
DATA TRANSFERRED (N BYTES + ACKNOWLEDGE)
Figure 16. I2C--Master Transmitting Data to Slave
S
SLAVE ADDRESS
R/W
A
DATA
A
DATA
A
P
03615-017
1 = WRITE
DATA TRANSFERRED (N BYTES + ACKNOWLEDGE
Figure 17. I2C--Master Reading Data from Slave
S
SLAVE ADDRESS
R/W
A
DATA
A/A
S
SLAVE ADDRESS
R/W
A
DATA
A/A
P
READ OR WRITE
(N BYTES + ACKNOWLEDGE)
REPEATED START
READ OR WRITE
(N BYTES + ACKNOWLEDGE)
03615-018
DIRECTION OF TRANSFER MAY CHANGE AT THIS POINT
Figure 18. Combined Transmit/Read
Rev. A | Page 10 of 20
ADN2860
EEPROM INTERFACE
S 1 0 1 0 0 A 1 E A 0 E 0 A MEMORY ADDRESS A MEMORY DATA A MEMORY DATA A/A P
EEPROM SLAVE ADDRESS 0 WRITE
(N BYTES + ACKNOWLEDGE)
Figure 19. EEPROM Write
S
1
0
1
0
0
A 1 E
A 0 E
0
A
MEMORY DATA
A
MEMORY DATA
A
P
EEPROM SLAVE ADDRESS 1 READ
(N BYTES + ACKNOWLEDGE)
Figure 20. EEPROM Current Read
S
SLAVE ADDRESS
W
A
MEMORY ADDRESS
A
S
SLAVE ADDRESS
R
A
MEMORY DATA
A/A
P
03615-021
0 WRITE
REPEATED START
1 READ
(N BYTES + ACKNOWLEDGE)
Figure 21. EEPROM Random Read
The 256 bytes of EEPROM memory provided in the ADN2860 are organized into 16 pages of 16 bytes each. The word size of each memory location is one byte wide. The I2C slave address of the EEPROM is 10100(A1E)(A0E), where A1E and A0E are external pin-programmable address bits. The 2-pin programmable address bits allow a total of four ADN2860 devices to be controlled by a single I2C master bus, each having its own EEPROM. An internal 8-bit address counter for the EEPROM is automatically incremented following each read or write operation. For read operations, the address counter is incremented after each byte is read, and the counter rolls over from Address 255 to 0. For write operations, the address counter is incremented after each byte is written. The counter rolls over from the highest address of the current page to the lowest address of the current page. For example, writing two bytes beginning at Address 31 causes the counter to roll back to Address 16 after the first byte is written; then the address increments to 17 after the second byte is written.
than 16 bytes of data are sent in a single write operation, the address counter rolls back to the beginning address, and the previously sent data is overwritten.
EEPROM Write-Acknowledge Polling
After each write operation, an internal EEPROM write cycle begins. During the EEPROM internal write cycle, the I2C interface of the device is disabled. It is necessary to determine if the internal write cycle is complete and whether the I2C interface is enabled. To do so, execute I2C interface polling by sending a start condition, followed by the EEPROM slave address plus the desired R/W bit. If the ADN2860 I2C interface responds with an ACK, the write cycle is complete and the interface is ready to proceed with further operations. Otherwise, the I2C interface must be polled again to determine whether the write cycle has been completed.
EEPROM Read
The ADN2860 EEPROM provides two different read operations, shown in Figure 20 and Figure 21. The number of bytes, N, read from the EEPROM in a single operation is unrestricted. If more than 256 bytes are read, the address counter rolls back to the start address, and data previously read is read again. Figure 20 shows the EEPROM current read operation. This operation does not allow an address location to be specified, and reads data beginning at the current address location stored in the internal address counter.
EEPROM Write
Each write operation issued to the EEPROM programs between 1 byte and 16 bytes (one page) of memory. Figure 19 shows the EEPROM write interface. The number of bytes of data, N, that the user wants to send to the EEPROM is unrestricted. If more
Rev. A | Page 11 of 20
03615-020
03615-019
ADN2860
A random read operation is shown in Figure 21. This operation changes the address counter to the specified memory address by performing a dummy write and then performing a read operation beginning at the new address counter location.
EEPROM Write Protection
Setting the WP pin to logic low protects the EEPROM memory from future write operations. In this mode, EEPROM read operations and RDAC register loading operate normally.
RDAC I2C INTERFACE
S 0 1 0 1 1 A 1 R A 0 R 0 A CMD/ REG 0 EE/ RD AC A 4 A 3 A 2 A 1 A 0 A DATA A DATA A/A P
RDAC SLAVE ADDRESS 0 WRITE
RDAC ADDRESS
(N BYTES + ACKNOWLEDGE)
Figure 22. RDAC Write
S
0
1
0
1
1
A 1 R
A 0 R
1
A
RDAC EEPROM OR REGISTER DATA
A
RDAC EEPROM OR REGISTER DATA
A
P
RDAC SLAVE ADDRESS 1 READ
(N BYTES + ACKNOWLEDGE)
Figure 23. RDAC Current Read
S
SLAVE ADDRESS
W
A
RDAC ADDRESS
A
S
SLAVE ADDRESS
R
A
RDAC DATA
A/A
P
03615-024
0 WRITE
REPEATED START
1 READ
(N BYTES + ACKNOWLEDGE)
Figure 24. RDAC Random Read
S
0
1
0
1
1
A 1 R
A 0 R
0
A
CMD/ REG
C 3
C 2
C 1
C 0
A 2
A 1
A 0
A
P
RDAC SLAVE ADDRESS 0 WRITE 1 CMD
Figure 25. RDAC Shortcut Commands
Table 5. RDAC Register Addresses (CMD/REG = 0, EE/RDAC = 0)
A4 0 0 0 0 0 0 1 A3 0 0 0 0 0 0 1 A2 0 0 0 0 1 1 ...to... 1 A1 0 0 1 1 0 0 1 A0 0 1 0 1 0 1 1 RDAC RDAC0 RDAC0 RDAC1 RDAC1 RDAC2 Byte Description (D7)(D6)(D5)(D4)(D3)(D2)(D1)(D0)--RDAC0 8 LSBs (X)(X)(X)(X)(X)(X)(X)(D8)--RDAC0 MSB (D7)(D6)(D5)(D4)(D3)(D2)(D1)(D0)--RDAC1 8 LSBs (X)(X)(X)(X)(X)(X)(X)(D8)--RDAC1 MSB (X)(D6)(D5)(D4)(D3)(D2)(D1)(D0)--RDAC2 7 bits Reserved
Rev. A | Page 12 of 20
03615-025
03615-023
03615-022
ADN2860
Table 6. RDAC R/W EEPROM Addresses (CMD/ REG = 0, EE/RDAC = 1)
A4 0 0 0 0 0 0 0 A3 0 0 0 0 0 0 1 A2 0 0 0 0 1 1 ...to... 1 A1 0 0 1 1 0 0 1 A0 0 1 0 1 0 1 1 Byte Description RDAC0 8 LSBs RDAC0 MSB RDAC1 8 LSBs RDAC1 MSB RDAC2 7 bits 11 bytes RDAC user EEPROM
Table 7. RDAC Command Table (CMD/REG = 1)
C3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 C2 0 0 0 0 1 1 1 1 0 0 0 0 1 ...to... 1 C1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 C0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Command Description NOP. Restore EEPROM to RDAC.1 Store RDAC to EEPROM.2 Decrement RDAC 6 dB. Decrement all RDACs 6 dB. Decrement RDAC one step. Decrement all RDACs one step. Reset. Restore EEPROM to all RDACs.2 Increment RDAC 6 dB. Increment all RDACs 6 dB. Increment RDAC one step. Increment all RDACs one step. Reserved.
1 2
Command leaves the device in the EEPROM read power state. Issue the NOP command to return the device to the idle state. Command requires acknowledge polling after execution.
RDAC Interface Operation
Each programmable resistor wiper setting is controlled by specific RDAC registers, as shown in Table 5. Each RDAC register corresponds to an EEPROM memory location, which provides nonvolatile wiper storage functionality. RDAC registers and their corresponding EEPROM memory locations are programmed and read independently from each other. The RDAC register is refreshed by the EEPROM locations, either with a hardware reset via Pin 1, or by issuing one of the various RDAC register load commands shown in the Table 7. As with the EEPROM write operation, any RDAC EEPROM (Shortcut Command 2) write operation disables the I2C interface during the internal write cycle. Acknowledge polling, as described in the EEPROM Interface section, is required to determine whether the write cycle is complete.
RDAC Read
The ADN2860 provides two RDAC read operations. The first, shown in Figure 23, reads the contents of the current RDAC address counter. Figure 24 illustrates the second read operation, which allows users to specify which RDAC register to read by first issuing a dummy write command to change the RDAC address pointer, and then proceeding with the RDAC read operation at the new address location. The read-only RDAC EEPROM memory locations can also be read by using the address and bits specified in Table 6.
RDAC Write
Setting the wiper position requires an RDAC write operation, shown in Figure 22. RDAC write operations follow a format similar to the EEPROM write interface. The only difference between an RDAC write and an EEPROM write operation is the use of an RDAC address byte in place of the memory address used in the EEPROM write operation. The RDAC address byte is described in detail in Table 5 and Table 6.
Rev. A | Page 13 of 20
ADN2860
RDAC Shortcut Commands
Eleven shortcut commands are provided for easy manipulation of RDAC registers and their corresponding EEPROM memory locations. These commands are shown in Table 9. A more detailed discussion about the RDAC shortcut commands can be found in the Theory of Operation section. The interface for issuing an RDAC shortcut command is shown in Figure 25. All shortcut commands require acknowledge polling to determine whether the command has finished executing.
RDAC Resistor Tolerance
The end-to-end resistance tolerance for each RDAC channel is stored in read-only memory during factory production. This information is read by using the address and bits specified in Table 8. Tolerance values are stored in percentage form. Figure 26 shows the format of the tolerance data stored in memory. Each stored tolerance uses two memory locations. The first location stores the integer portion, while the second location stores the decimal portion. The resistance tolerance is stored in sign-magnitude format. The MSB of the first memory location designates the sign (0 = +, 1 = -) and the remaining 7 LSBs are designated for the integer portion of the tolerance. All eight bits of the second memory location are represented by the decimal portion of the tolerance value.
Table 8. Addresses for Reading Tolerance (CMD/REG = 0, EE/RDAC = 1, A4 = 1)
A4 1 1 1 1 1 1 A3 1 1 1 1 1 1 A2 0 0 0 0 1 1 A1 0 0 1 1 0 0 A0 0 1 0 1 0 1 Data Byte Description Sign and 7-bit integer values of RDAC0 tolerance (read only) 8-bit decimal value of RDAC0 tolerance (read only) Sign and 7-bit integer values of RDAC1 tolerance (read only) 8-bit decimal value of RDAC1 tolerance (read only) Sign and 7-bit integer values of RDAC2 tolerance (read only) 8-bit decimal value of RDAC2 tolerance (read only)
A
D7 SIGN
D6 26
D5 25
D4 24
D3 23
D2 22
D1 21
D0 20
A
D7 2-1
D6 2-2
D5 2-3
D4 2-4
D3 2-5
D2 2-6
D1 2-7
D0 2-8
A
SIGN
7 BITS FOR INTEGER NUMBER
8 BITS FOR DECIMAL NUMBER
Figure 26. Format of Stored Tolerance in Sign Magnitude with Bit Position Descriptions (Unit is in %, Only Data Bytes Shown)
Rev. A | Page 14 of 20
03615-026
ADN2860 THEORY OF OPERATION
The ADN2860 digital potentiometer operates as a true variable resistor. The RDAC register contents determine the resistor wiper position. The RDAC register acts like a scratchpad register, allowing unlimited resistance setting changes. RDAC register contents are changed using the ADN2860's serial I2C interface. See the RDAC I2C Interface section for the format of the data words and commands to program the RDAC registers. Each RDAC register has a corresponding EEPROM memory location, which provides nonvolatile storage of resistor wiper position settings. The ADN2860 provides commands to store the RDAC register contents to their respective EEPROM memory locations. During subsequent power-on sequences, the RDAC registers are automatically loaded with the stored values. Saving data from an RDAC register to EEPROM memory takes approximately 25 ms and consumes 35 mA. In addition to moving data between RDAC registers and EEPROM memory, the ADN2860 provides other shortcut commands. Table 9. ADN2860 Shortcut Commands
No. Function 1 Restore EEPROM setting to RDAC1 2 Store RDAC register contents to EEPROM2 3 Decrement RDAC 6 dB (shift data bits right) 4 Decrement all RDACs 6 dB (shift all data bits right) 5 Decrement RDAC one step 6 Decrement all RDACs one step 7 Reset EEPROM setting to RDAC2 8 Increment RDAC 6 dB (shift data bits left) 9 Increment all RDACs 6 dB (shift all data bits left) 10 Increment RDAC one step 11 Increment all RDACs one step __________________________
1 2
LOGARITHMIC TAPER MODE ADJUSTMENT (6 dB/STEP)
The ADN2860 accommodates logarithmic taper adjustment of the RDAC wiper position(s) by shifting the register contents left/right for increment/decrement operations. Commands 8, 9, 3, and 4 are used to logarithmically increment or decrement the wiper positions individually or change all three channel settings at the same time. Incrementing the wiper position by +6 dB doubles the RDAC register value, whereas decrementing by -6 dB halves it. Internally, the ADN2860 uses a shift register to shift the bits left and right to achieve a logarithmic increment or decrement. Nonideal 6 dB step adjustment occurs under certain conditions. Table 10 illustrates how the shifting function affects the data bits of an individual RDAC. Each row going down the table represents a successive shift operation. Note that the left-shift commands (Commands 10 and 11) were modified such that if the data in the RDAC register equals 0 and the data is shifted, the RDAC register is set to Code 1. Similarly, if the data in the RDAC register is greater than or equal to midscale and the data is left shifted, the data in the RDAC register is automatically set to full scale. This makes the left-shift function as close as possible to a logarithmic adjustment. The right-shift commands (Commands 3 and 4) are ideal only if the LSB is a 0 (ideal logarithmic = no error). If the LSB is 1, the right-shift function generates a linear half LSB error. Table 10. RDAC Register Contents after 6 dB Step Adjustments
Left Shift (+6 dB/Step) 0 0000 0000 0 0000 0001 0 0000 0010 0 0000 0100 0 0000 1000 0 0001 0000 0 0010 0000 0 0100 0000 0 1000 0000 1 0000 0000 1 1111 1111 1 1111 1111 Right Shift (-6 dB/Step) 1 1111 1111 0 1111 1111 0 0111 1111 0 0011 1111 0 0001 1111 0 0000 1111 0 0000 0111 0 0000 0011 0 0000 0001 0 0000 0000 0 0000 0000
Command leaves the device in the EEPROM read power state. Issue the NOP command to return the device to the idle state. Command requires acknowledge polling after execution.
LINEAR INCREMENT AND DECREMENT COMMANDS
The increment and decrement commands (Commands 10, 11, 5, and 6) are useful for linear step adjustment applications. These commands simplify microcontroller software coding by allowing the controller to send only an increment or decrement command to the ADN2860. The adjustment can be directed to an individual RDAC or to all three RDACs.
Actual conformance to a logarithmic curve between the data contents in the RDAC register and the wiper position for each right-shift command (Commands 3 and 4) execution contains an error only for odd numbers of bits. Even numbers of bits are ideal. Figure 26 shows a plot of Log_Error, that is, 20 x Log10(error/code), for the ADN2860.
Rev. A | Page 15 of 20
ADN2860
USING ADDITIONAL INTERNAL NONVOLATILE EEPROM
The ADN2860 contains additional internal user EEPROM for saving constants and other data. The user EEPROM I2C dataword follows the same format as the general-purpose EEPROM memory shown in Figure 19 and Figure 20. User EEPROM memory addresses are shown in Table 6. To support the use of multiple EEPROM modules on a single I2C bus, the ADN2860 features two external addressing pins, Pins 21 and 22 (A1_EE and A0_EE), to manually set the address of the EEPROM included with the ADN2860. This feature ensures that the correct EEPROM memory is accessed when using multiple memory modules on a single I2C bus.
LEVEL SHIFT FOR BIDIRECTIONAL COMMUNICATION
While most legacy systems operate at one voltage, adding a new component might require a different voltage. When two systems transmit the same signal at two different voltages, use a level shifter to allow the systems to communicate. For example, a 3.3 V microcontroller (MCU) can be used along with a 5 V digital potentiometer. A level shifter is required to enable bidirectional communication. Figure 29 shows one of many possible techniques to properly level-shift signals between two devices. M1 and M2 are N-channel FETs (2N7002). If VDD falls below 2.5 V, use low threshold N-channel FETs (FDV301N) for M1 and M2.
VDD1 = 3.3V RP RP G
SDA1
DIGITAL INPUT/OUTPUT CONFIGURATION
All digital inputs are ESD protected. Digital inputs are high impedance and can be driven directly from most digital sources. The RESET digital input pin does not have an internal pull-up resistor. Therefore, the user should place a pull-up resistor from RESET to VDD if the function is not used. The WP pin has an internal pull-down resistor. If not driven by an external source, the ADN2860 defaults to a write-protected state. ESD protection of the digital inputs is shown in Figure 27.
VDD
VDD2 = 5V RP RP
S M1
D G S M2 D
SDA2
SCL1
SCL2
Figure 29. Level Shifting for Different Voltage Devices on an I2C Bus
INPUTS WP
TERMINAL VOLTAGE OPERATION RANGE
The ADN2860 positive VDD and negative VSS power supply inputs define the boundary conditions for proper 2-terminal programmable resistance operation. Supply signals on Terminals W and B that exceed VDD or VSS are clamped by the internal forward-biased diodes of the ADN2860.
VDD
GND
Figure 27. Equivalent WP ESD Protection
MULTIPLE DEVICES ON ONE BUS
Figure 28 shows four ADN2860 devices on the same serial bus. Each has a different slave address because the state of their AD0 and AD1 pins are different. This allows independent reading and writing to each RDAC within each device.
+5V RP RP
A W B
03615-030
03615-027
VSS
Figure 30. Maximum Terminal Voltages Set by VDD and VSS
SDA
MASTER SCL VDD SDA SCL AD1 AD0 SDA SCL AD1 AD0 VDD SDA SCL AD1 AD0 VDD SDA SCL AD1
03615-028
The ground pin of the ADN2860 is used as a digital ground reference and needs to be tied to the common ground of the PCB. Reference the digital input control signals to the ADN2860 ground pin and satisfy the logic levels defined in Table 1 and Table 2.
AD0
Figure 28. Multiple ADN2860 Devices on a Single Bus
Rev. A | Page 16 of 20
03615-029
3.3V MCU
5V ADN2860
ADN2860
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance at the A, B, and W terminals (Figure 30), it is important to power VDD/VSS before applying voltage to the A, B, and W terminals. Otherwise, the diode is forward biased such that VDD/VSS are powered unintentionally, which affects the rest of the circuit. The ideal power-up sequence is as follows: GND, VDD, VSS, digital inputs, and VA/B/W. The order of powering VA, VB, VW, and the digital inputs is not important, as long as they are powered after VDD/VSS. Since the switches are nonideal, there is a 100 wiper resistance, RW. Wiper resistance is a function of supply voltage and temperature; lower supply voltages and higher temperatures result in higher wiper resistances. Consideration of wiper resistance dynamics is important in applications in which accurate prediction of output resistance is required.
SWA AX SW(2N-1)
LAYOUT AND POWER SUPPLY BIASING
It is always a good practice to use compact, minimum-leadlength layout design. Make the leads to the input as direct as possible with a minimum conductor length. Make sure that ground paths have low resistance and low inductance. It is also a good practice to bypass the power supplies with quality capacitors. Use low equivalent series resistance (ESR) 1 F to 10 F tantalum or electrolytic capacitors at the supplies to minimize any transient disturbance and filter low frequency ripple. Figure 31 illustrates the basic supply-bypassing configuration for the ADN2860.
VDD + C3 10F + C4 10F VSS C1 0.1F GND C2 0.1F VSS
03615-031
RDAC WIPER REGISTER AND DECODER
RS
SW(2N-2)
WX
RS
SW(1)
RS = RAB/2N DIGITAL CIRCUITRY OMITTED FOR CLARITY
RS
SW(0)
BX
VDD
ADN2860
Figure 32. Equivalent RDAC Structure
CALCULATING THE PROGRAMMABLE RESISTANCE
The nominal resistance of the RDAC between the A and B terminals is available in 25 k or 250 k. The final two or three digits of the part number determine the nominal resistance value, for example, 25 k = 25 and 250 k = 250. The following discussion describes the calculation of resistance RWB(d) at different codes of a 25 k part for RDAC0. The 9-bit data-word in the RDAC latch is decoded to select one of the 512 possible settings. The first wiper connection starts at the B terminal for data 0x000. RWB(0) is 100 of the wiper resistance and is independent of the full-scale resistance. The second connection is the first tap point where RWB(1) becomes 48.8 + 100 = 148.8 for data 0x001. The third connection is the next tap point representing RWB(2) = 97.6 + 100 = 197.6 for data 0x002, and so on. Each LSB data-value increase moves the wiper up the resistor ladder until the last tap point is reached at RWB(511) = 25,051 . See Figure 32 for a simplified diagram of the equivalent RDAC circuit. These general equations determine the programmed output resistance between terminals W and B.
Figure 31. Power Supply Bypassing
Solder the slug on the bottom of the LFCSP package to a floating pad to improve thermal dissipation. Do not connect the slug to a ground plane on the PCB.
RDAC STRUCTURE
The patent pending RDAC contains a string of equal resistor segments with an array of analog switches. The switches together act as the wiper connection. The ADN2860 has two RDACs with 512 connection points, allowing it to provide better than 0.2% progammability resolution. The ADN2860 also contains a third RDAC with 128-step resolution. Figure 32 shows an equivalent structure of the connections between the two terminals that make up one channel of an RDAC. The SWB switch is always on, while one of switches SW(0) to SW(2N - 1) may or may not be on at any given time, depending on the resistance position decoded from the data bits in the RDAC register.
Rev. A | Page 17 of 20
03615-032
SWB
ADN2860
For RDAC0 and RDAC1:
RWB (D ) = D x R AB + RW 512
(1)
For example, the following RDAC latch codes set the corresponding output resistance values, which apply to RAB = 25 k digital potentiometers. Table 12. RWA(d) at Selected Codes for RAB = 25 k
D (DEC) 511 256 1 0 RWA(d) () 148.8 12600 25051 25100 Output State Full scale Midscale 1 LSB Zero scale
For RDAC2:
RWB (D ) = D x R AB + RW 128
(2)
where: D is the decimal equivalent of the data contained in the RDAC register. RW is the wiper resistance. The output resistance values in Table 11 are set for the given RDAC latch codes with VDD = 5 V, which applies to RAB = 25 k digital potentiometers. Table 11. RWB at Selected Codes for RWB_FS = 25 k
D (DEC) 511 256 1 0 RWB(d) () 25051 12600 148.8 100 Output State Full scale Midscale 1 LSB Zero scale (wiper contact resistance)
The typical distribution of RAB from channel to channel is 0.1% within the same package. Device-to-device matching is lot dependent, with a worst-case variation of 15%. RAB temperature coefficient is 35 ppm/C.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer can be configured to generate an output voltage at the wiper terminal, which is proportional to the input voltages applied to the A and B terminals. Connecting the A terminal to 5 V and the B terminal to ground produces an output voltage at the wiper that can vary between 0 V to 5 V. Each LSB of voltage is equal to the voltage applied across the A and B terminals divided by the 2N position resolution of the potentiometer divider. Since the ADN2860 can operate from dual supplies, the general equations defining the output voltage at VW with respect to ground for any given input voltages applied to the A and B terminals are as follows: For RDAC0 and RDAC1:
VW (D ) = D x VAB + VB 512
Note that in the zero-scale condition, a finite wiper resistance of 100 is present. To avoid degradation or possible destruction of the internal switches, care should be taken to limit the current flow between Terminals W and B to no more than 20 mA intermittently or 2 mA continuously. Channel-to-channel RWB matching is better than 0.1%. The change in RWB with temperature has a 35 ppm/C temperature coefficient. Like the mechanical potentiometer that the RDAC replaces, the ADN2860 parts are totally symmetrical. The resistance between the W wiper and the A terminal also produces a digitally controlled complementary resistance, RWA. When RWA is used, the B terminal can be floating or tied to the wiper. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch is increased in value. The general transfer equations for this operation are as follows: For RDAC0 and RDAC1:
RWB (D ) = 512 - D 512 x R AB + RW
(5)
For RDAC2:
VW (D ) = D x V AB + VB 128
(6)
(3)
Equation 5 assumes that VW is buffered to null the effect of wiper resistance. Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. In this mode, the output voltage is dependent on the ratio of the internal resistors, not on the absolute value; therefore, the drift improves to 15 ppm/C. There is no voltage polarity restriction between the A, B, and W terminals as long as the terminal voltage (VTERM) stays within VSS < VTERM < VDD.
For RDAC2:
RWB (D ) = 128 - D 128 x R AB + RW
(4)
Rev. A | Page 18 of 20
ADN2860 APPLICATIONS
LASER DIODE DRIVER (LDD) CALIBRATION
The ADN2860 can be used with any laser diode driver. Its high resolution, compact footprint, and superior temperature drift characteristics make it ideal for optical parameter setting. The ADN2841 is a 2.7 Gbps laser diode driver that uses a unique control algorithm to manage both the laser average power and extinction ratio after initial factory calibration. It stabilizes the laser data transmission by continuously monitoring its optical power and by correcting the variations caused by temperature and the laser degradation over time. In the ADN2841, the IMPD monitors the laser diode current. Through its dual-loop power and extinction ratio control, calibrated by the ADN2860, the internal driver controls the bias current, IBIAS, and, consequently, the average power. It also regulates the modulation current, IMODP, by changing the modulation current linearly with slope efficiency. Any changes in the laser threshold current or slope efficiency are, therefore, compensated. As a result, this optical supervisory system minimizes the laser characterization efforts, enabling designers to apply comparable lasers from multiple sources.
VCC VCC
ADN2860
PSET SDA SCL ERSET
ADN2841
Figure 33. Optical Supervisory System
Rev. A | Page 19 of 20
03615-033
ASET
ADN2860 OUTLINE DIMENSIONS
4.00 BSC SQ 0.60 MAX 0.60 MAX
19 18 EXPOSED PAD
(BOTTOM VIEW)
PIN 1 INDICATOR
24 1
PIN 1 INDICATOR
TOP VIEW
3.75 BSC SQ
0.50 BSC 0.50 0.40 0.30
2.25 2.10 SQ 1.95
7 6
13 12
0.25 MIN 2.50 REF
1.00 0.85 0.80
12 MAX
0.80 MAX 0.65 TYP
0.05 MAX 0.02 NOM 0.20 REF COPLANARITY 0.08
SEATING PLANE
0.30 0.23 0.18
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
Figure 34. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm x 4 mm Body (CP-24-1) Dimensions shown in millimeters
ORDERING GUIDE
Model ADN2860ACPZ25-RL71 ADN2860ACPZ250-RL71 ADN2860-EVAL Temperature Range -40C to +85C -40C to +85C Package Description Lead Frame Chip Scale Package Lead Frame Chip Scale Package Evaluation Board Package Option CP-24-1 CP-24-1 Full Container Quantity 1,500 1,500 RAB (k) 25 250
1
Z = Pb-free part.
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03615-0-11/04(A)
Rev. A | Page 20 of 20
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